Currently, a random access of a memory controller to a dynamic random access memory (DRAM) is affected by inherent parameters (see Table 1) of the DRAM. A periodic interval exists between written commands. This periodic interval, however, causes a bus to be idle.
TABLE 1DDR3-1600ParameterDescriptionInfluenceParameter ValueCLClock period from sending anRead delay11 cyclesRD/RDAP command in aDRAM to outputting dataALPeriodic interval from sending Improvement ofMay be set to 0, an RD/RDAP command orcommand busCL-1, or CL-2WR/WRAP command on autilizationDRAM bus until the commandis valid in the interiortRCACT-to-ACT periodic intervalPerformance of random48.75 nsfor access different Rows in aaccess in a BankBanktRRDACT-to-ACT periodic intervalPerformance of random7.5 nsbetween different Banksaccess at the time ofBank interleavingtFAWFour consecutive ACT commandPerformance of random40 nswindowsaccess at the time ofBank interleavingtRTPRD/RDAP-to-PRECHARGEPeriodic interval from a 7.5 nsperiodic intervalread operation to a nextrandom access in aBanktWRWrite recovery periodPeriodic interval from a 15 nswrite operation to anext random access in aBanktRPPRECHARGE periodPeriodic interval from a 13.75 nsread/write operation toa next random access ina BanktWTRPeriodic interval from receivingWrite-to-read delay7.5 nsan internal write command toreceiving an internal readcommand
Existing hardware architecture for implementing an access to a DRAM includes a memory controller and two X16 DDR3 memories (SDRAM, Synchronous Dynamic Random Access Memory). The two X16 DDR3 SDRAMs physically share address/command (ADDR/CMD) bus signals, and perform time-division multiplexing on ADDR/CMD bus signals in terms of a time sequence; each X16 DDR3 SDRAM uses an independent chip selection signal; and the input/output (IO) and data strobe (DQS) signals of each X16 DDR3 SDRAM are connected in “point-to-point” mode to the controller.
Based on the existing hardware architecture, a method for accessing a DRAM is generally as follows. A memory controller writes a row strobe command (ACT, ACTIVE) and a corresponding write operation command or read operation command into the DRAM, and then writes an ACT and a corresponding write operation command or read operation command, which are repeated to implement an access to the DRAM. An ACT command is a row strobe command of a DRAM. Its function is to activate a bank (Bank) in the DRAM, so as to write a read command or a write command into the activated Bank. Due to the existence of inherent parameters of a DRAM, a certain periodic interval exists between commands. This periodic interval, however, causes a bus to be idle. An example is taken for illustration in the following.
For example, a DRAM of a network device is used to implement a table lookup (Table lookup) function. Because a lookup table is composed of several lookup entries, for a random access to preceding and following entries, a situation that different rows (Row) of the same Bank of the DRAM are searched may occur, which is limited by a tRC, leaving multiple idle clock periods between lookup commands of the two entries.
To improve DRAM bandwidth utilization, generally, a lookup table is duplicated to multiple Banks and a next Bank is switched to after each entry lookup, so as to avoid the occurrence of the tRC by consecutively accessing multiple Banks. Because a row strobe command (ACT) needs to be sent for each lookup, a method of using multiple Banks to duplicate a lookup table and consecutively accessing multiple Banks will bring the tRRD and tFAW, although the tRC may be avoided.
If a DRAM is used as a packet buffer, generally a method of “multi-Bank rotary writing+multi-Bank rotary reading” is used to utilize the tRC and reduce a “read-to-write” idle period and a “write-to-read” idle period. However, as the working frequency increases, to avoid an influence brought by the tRRD and tFAW, the length of each Bank needs to be increased, causing a decrease in memory utilization when a memory stores messages. In addition, because of being affected by the CL and tWTR, a “write-to-read” idle period will be greatly increased, lowering the bandwidth utilization of the DRAM.
When the dominant frequency of a DRAM granule is improved to a DDR3-2133 or a DDR4 component of a higher frequency, the tWTR and CL will increase to more DRAM clock periods, causing even lower DRAM bandwidth utilization. In addition, to meet the tRRD and tFAW parameters, each cell needs to be configured to a larger size, for example, is configured to a size of three burst lengths (BL, Burst Length) or four BL8s. When the size of a Cell is three BL8s, for each X16 DDR3 SDRAM component, each BL8 is 32 bytes (Bytes), so that each Cell is 96 Bytes. Generally, each Cell can only be used to store one message. When a Cell fails to store one message, multiple Cells may store one message. For a message of 64 Bytes, one Cell needs to be allocated to store the message. In this case, the utilization of a DRAM is only 66.7% (64/96), forming a so-called small cell “N+1” problem. The larger a Cell is, the severer the small cell “N+1” problem is, that is, the lower the utilization of a DRAM is.
Based on the current hardware architecture, the prior art fails to decouple an ACT from a corresponding operation command under the premise of guaranteeing the bandwidth utilization of a DRAM, and therefore fails to flexibly invoke a command and fails to further avoid an influence brought by inherent parameters of the DRAM. As a result, a memory bandwidth cannot be further improved.